1. Field of the Invention
The present invention relates to a bipolar transistor, more particularly to a bipolar transistor suitable for high-frequency and high-speed operation, in which its extrinsic base region has a twin well structure adapted to reduce base resistance. The present invention also relates to a method for manufacturing such a bipolar transistor.
2. Description of the Related Art
As well known to those skilled in the art, a bipolar transistor is generally a semiconductor device having two PN junctions between a base and collector and between a base and an emitter on a silicon substrate, so as to carry out switching and amplifying functions.
Among bipolar transistors, a high-frequency bipolar transistor requires high current gain and low base resistance to improve low noise characteristic. In order to achieve this goal, some approaches employ a base region comprising an intrinsic base region of low density and an extrinsic base region of high density and thin junction depth, which is formed on the intrinsic base region. With the aforementioned configuration, low noise characteristic at high-speed performance can be improved by obtaining high current gain through the intrinsic base region and supplying base current through the extrinsic base region.
FIG. 1a is a partial cross-sectional view of a conventional bipolar transistor. As shown in FIG. 1a, the conventional bipolar transistor of NPN type includes a collector region having a high-density N-type silicon substrate 11 and a low-density N-type epitaxial layer 12 formed on the silicon substrate 11, a base region having an intrinsic base region 15, which is low-density doped with P-type dopant, and an extrinsic base region 16, which is high-density doped with P-type dopant on the intrinsic base region 15, and an emitter region 18, which is doped with N-type dopant on the intrinsic base region 15. Although not shown in FIG. 1a, an oxidation layer is formed on the uppermost surface and partially opened to form an emitter electrode and a base electrode with poly silicon or metal. Additionally, a collector electrode is formed on the lower surface of the silicon substrate 11.
The conventional bipolar transistor of FIG. 1a operates in such a manner that when base current is supplied to the base electrode, amplified collector current in proportion with the amplification degree of the base current flows into the emitter region. Herein, it is preferable to increase the current gain, i.e., the ratio of the collector current to the base current. However, as represented by arrows in FIG. 1a, the base current flows into not only the emitter region but also the collector region through the intrinsic base region. Parts of the base current flowing into the base region increase the base resistance, thereby reducing the current gain.
The aforementioned problem occurs also in a bipolar transistor with an up-collector structure. FIG. 1b is a partial cross-sectional view of the conventional NPN-type bipolar transistor with an up-collector structure. As shown in FIG. 1b, the conventional NPN-type bipolar transistor includes a silicon substrate 21, a base region including an intrinsic base region 25, which is low-density doped with P-type dopant, and an extrinsic base region 26, which is high-density doped with P-type dopant, an emitter region 28, which is doped with N-type dopant on the intrinsic base region 25, and a high-density N-type collector region 22 formed on the intrinsic base region 25.
With this structure, parts of the collector current generated from the collector region 22 flow into the substrate 21, thereby reducing the collector current efficiency and increasing the collector resistance and inductance.
The current generated from the base region (or from the collector region of the up-collector structure) flows in an undesired direction and reduces the low-noise characteristic at high-frequency and high-speed performance and Va (early voltage) for modulating the base depth, thus hampering the performance of the bipolar transistor.
Therefore, a bipolar transistor with an innovative and novel structure to maximize the current gain is required so as to improve the performance at high-frequency and high-speed operation.
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a bipolar transistor having an improved performance at the high-frequency and high-speed operation by forming the base or the collector in a twin well structure so as to decrease the current flowing in an undesired direction.
It is another object of the present invention to provide a method for manufacturing a bipolar transistor to maximize the current gain.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a bipolar transistor comprising a collector region including a semiconductor substrate doped with a first conductive dopant, an intrinsic base region low-density doped with a second conductive dopant on the semiconductor substrate, the second conductive dopant being contrary to the first conductive dopant, an extrinsic base region high-density doped with the second conductive dopant on a first portion of the upper surface of the intrinsic base region and formed in a single well with at least two branched lower terminals, an emitter region doped with the first conductive dopant on a second portion of the upper surface of the intrinsic base region, the second portion spaced from the first portion by a designated interval, a collector electrode formed on the lower surface of the semiconductor substrate, an emitter electrode formed on the upper surface of the emitter region, and a base electrode formed on the upper surface of the extrinsic base region.
Preferably, the emitter region may be spaced from both sides of the extrinsic base region by a designated interval, and the single well of the extrinsic base region may be a twin well structure with lower terminals branched into the emitter region.
Further, preferably, the semiconductor substrate may include a substrate high-density doped with the first conductive dopant, and an epitaxial layer low-density doped with the first conductive dopant on the upper surface of the substrate.
In accordance with another aspect of the present invention, there is provided a bipolar transistor comprising
a semiconductor substrate, an intrinsic base region low-density doped with a first conductive dopant on the upper surface of the semiconductor substrate, a collector region doped with a second conductive dopant on a first portion of the upper surface of the intrinsic base region and formed in a single well with at least two branched lower terminals, an extrinsic base region doped with the first conductive dopant on a second portion of the upper surface of the intrinsic base region and, the second portion spaced from the first portion by a designated interval, an emitter region doped with the second conductive dopant on a third portion of the upper surface of the intrinsic base region, the third portion spaced from the first portion and the second portion by a designated interval, a collector electrode formed on the upper surface of the collector region, an emitter electrode formed on the upper surface of the emitter region, and a base electrode formed on the upper surface of the extrinsic base region.
Preferably, the extrinsic base region may be spaced from both sides of the collector region by a designated interval, and the single well of the collector region is a twin well structure with lower terminals branched into the emitter region.
In accordance with yet another aspect of the present invention, there is provided a method for manufacturing a bipolar transistor. The bipolar transistor manufacturing method includes the steps of forming a semiconductor substrate doped with a first conductive dopant, forming an intrinsic base region low-density doped with a second conductive dopant on the semiconductor substrate, the second conductive dopant being contrary to the first conductive dopant, forming an extrinsic base region high-density doped with the second conductive dopant on a first portion of the upper surface of the intrinsic base region and formed in a single well with at least two branched lower terminals, forming an emitter region doped with the first conductive dopant on a second portion of the upper surface of the intrinsic base region, the second portion spaced from the first portion by a designated interval, and forming a collector electrode, an emitter electrode and a base electrode on the lower surface of the semiconductor substrate, the upper surface of the emitter region and the upper surface of the extrinsic base region, respectively.
Preferably, the step of forming the semiconductor substrate may include the sub-steps of forming a substrate high-density doped with the first conductive dopant, and forming an epitaxial layer low-density doped with the first conductive dopant on the upper surface of the substrate.
Further, preferably, the step of forming the extrinsic base region includes the sub-steps of forming two separated wells by being doped with the second conductive dopant using a mask provided with two separated openings corresponding two wells, and forming an extrinsic base region of a twin well structure by diffusing the two separated wells.